FPGA Targets
List available targets with ssynth targets or the Targets tab on any project page.
iCE40 Family
Open-source toolchain: Yosys + nextpnr-ice40 + icepack.
| Target ID | Device | Package | LUTs |
|---|---|---|---|
ice40:hx1k:tq144 | HX1K | TQFP-144 | 1,280 |
ice40:hx8k:ct256 | HX8K | CABGA-256 | 7,680 |
ice40:up5k:sg48 | UP5K | SG48 | 5,280 |
ECP5 Family
Open-source toolchain: Yosys + nextpnr-ecp5 + ecppack.
| Target ID | Device | Package | LUTs |
|---|---|---|---|
ecp5:25k:CABGA256 | LFE5U-25F | CABGA-256 | 24,288 |
ecp5:45k:CABGA381 | LFE5U-45F | CABGA-381 | 43,848 |
ecp5:85k:CABGA554 | LFE5U-85F | CABGA-554 | 83,640 |
Supported HDL Languages
| Language | Extensions |
|---|---|
| Verilog | .v |
| SystemVerilog | .sv |
| VHDL | .vhd, .vhdl |
Mixed Verilog/VHDL projects are supported. VHDL files are processed with GHDL before Yosys synthesis.
Constraint Files
| Family | Format | Extension |
|---|---|---|
| iCE40 | Physical Constraints | .pcf |
| ECP5 | Lattice Preference | .lpf |