Submitting Jobs (Web)
Create a job
- Navigate to a project
- Click New Job
- Fill in the required fields:
- Build Profile — optionally select a saved profile to pre-fill target and tool args
- Target — select an FPGA target (pre-filled if a profile is selected)
- Top Module — name of your top-level Verilog/VHDL module
- Source — drag-and-drop or browse for a
.tar.gzor.ziparchive of your HDL source
Advanced options
Expand the Advanced section to configure:
| Option | Default | Description |
|---|---|---|
| Seeds | 1 | Number of place-and-route seeds (1-64) |
| Strategy | best_timing | best_timing or best_area |
| Priority | standard | interactive, standard, or batch |
| Parallelism | 1 | How many seeds run concurrently (1-16) |
| Steps | all | Checkboxes: synth, pnr, bitstream |
| Max runtime | project default | Hours and minutes |
| Max memory | project default | GB or MB (up to 128 GB) |
- Click Create Job
You’re taken to the job detail page where you can watch progress in real time.
Source archives
Package your HDL source as a .tar.gz or .zip file. Include:
- All Verilog/SystemVerilog/VHDL source files
- Constraint files (
.pcf,.lpf) if needed - A
hwbuild.ymlis not required for web submissions (parameters are set in the form)
The archive should contain source files at the top level or in subdirectories. SuperSynth discovers .v, .sv, .vhd, and .vhdl files recursively.